Memory Hierarchy

Memory speeds have historically had an inverse nonlinear relationship to cost.

Great advances in memory capacity, speed, and cost have been made over the years, and there will be more in the future. However, the shape of the curve and the relative performance of the different technologies have remained essentially unchanged. Memory speeds that were the state of the art a few years ago are considered relatively slow today, and today’s state of the art will be commonplace in the future. The only certainty is that memory speeds and capacities will continue to increase and relative costs per byte of storage will continue to decrease.

The figure shows the components in a typical memory hierarchy. However, it depends on how the system actually designed. External memory is often split into two classes based on access speed. Programs and data that are regularly used by the system are typically stored online. With today’s technology this usually means the data is on fast disk devices.

Backup copies of important programs or data as well as programs and data that will not be needed soon are usually stored offline. On most systems this is usually some types of removable media such as magnetic tape or disk cartridges.

Need for Memory Hierarchy: IO processor manages data transfers between auxiliary memory and main memory. The cache organization is concerned with the transfer of information between main memory and CPU. Each is involved with a different level in the memory hierarchy system. The main reason for having two or three levels of memory hierarchy is economics.

As the storage capacity of the memory increases the cost per bit for storing binary information decreases and the access time of the memory becomes longer. Auxiliary memory has a large storage capacity, inexpensive but has low access speed compared to main memory. The cache memory is very small relatively expensive and has very high access speed. The overall goal of using a memory hierarchy is to obtain the highest possible average access speed while minimizing the total cost of the entire memory system.

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